While in operation, processors within computers continually access memory modules to store and retrieve data. Such memory modules include L1 and L2 caches, as well as Static Random Access Memory (SRAM) modules. To accomplish a memory access, an address to a specific wordline is first provided. Next, the address is decoded through a predecode and a final decode stage in order to determine the specific wordline to be activated. Once the selected wordline is activated, data from outside of a subarray of cells within the memory module is then written into the cells during a Write operation. Data written into the cells of the subarray comes out onto a bitline associated with the cells during a Read operation. Also during the Read operation, the bitline signal is detected by a sensing circuit having sense amplifiers, and the amplified signal is then captured by a read-out latch.
In high frequency memory, the total process is divided into many cycles. Since accessing small subarrays of cells is usually much faster than accessing a single large array, a large array is divided into many subarrays and cycle-bounded at the input, output, or both, of the subarrays for use in high speed memory modules. The bounding in these memory modules is typically provided by write data latches and read data latches.
In high speed memory modules, such as high frequency deep pipeline SRAMs, one memory access is accomplished in multiple pipeline cycles over short periods of time. For example, for decoding a wordline address, the predecode stage is one of these cycles and the final decode stage is another. Similarly, wordline activation to create data with the cells, as well as sense amplifier enabling to read data from bitlines, are further cycles in the pipeline process. Since many small subarrays are typically employed in place of a single large array, wordline and bitline loading is likewise smaller due to the decreased number of cells being accessed in each subarray. The reduction in wordline and bitline loading, in turn, results in wordline activation, bitline signal development and sensing, and capturing of the data. As a result, the final output signal generated fluctuates from high to low very quickly. Although cell access in multiple small subarrays improves overall memory access speed, overall timing management in large memory modules is typically difficult to govern.
Conventional timing circuitry employs control signals used by the subarray control circuitry received from outside the subarray. More specifically, an outside timing signal is typically used to govern the subarray control circuitry. Typically, enable information and launch timing comes into the subarray in the merged form. Unfortunately, the use of a control signal with timing from outside the subarray to control the circuitry is difficult to manage. More specifically, the timing of a subarray close to the source of the control signal is usually different from a distal subarray. In this conventional scheme, timing inside of both the near and far subarrays is interdependent, however, each needs to meet their own timing requirements.
Furthermore, the outside timing signal typically used in conventional designs must travel long distances before arriving at the subarray control circuit, leading to inaccuracies in the timing signal. Especially in high frequency deep pipeline memory, such inaccuracies are unacceptable. To combat this problem, buffers are often employed on the outside signal to maintain proper timing and to keep the waveform clean. However, the delay caused by the buffers to clean the timing signal can often prove detrimental to the timing involved in memory access cycles, especially in short cycle, high speed memory access, such as in high frequency deep pipeline SRAMs. Accordingly, a need exists for a subarray control circuit for use within high speed memory modules that does not suffer from the deficiencies found in conventional systems.